View CAT504_155002.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CAT504
8-Bit Quad DACpot
FEATURES
s Output settings retained without power s Output range includes both supply rails s 4 independently addressable outputs s 1 LSB Accuracy s Serial
APPLICATIONS
s Automated product calibration. s Remote control adjustment of equipment s Offset, gain and zero adjustments in Self-
Calibrating and Adaptive Control systems.
s Tamper-proof calibrations.
P interface
s Single supply operation: 2.7V-5.5V s Setting read-back without effecting outputs
DESCRIPTION The CAT504 is a quad 8-Bit Memory DAC designed as an electronic replacement for mechanical potentiometers and trim pots. Intended for final calibration of products such as camcorders, fax machines and cellular telephones on automated high volume production lines, it is also well suited for systems capable of self calibration, and applications where equipment which is either difficult to access or in a hazardous environment, requires periodic adjustment. The 4 independently programmable DAC's have an output range which includes both supply rails. Output settings, stored in non-volatile EEPROM memory, are not lost when the device is powered down and are automatically reinstated when power is returned. Each output can be dithered to test new output values without effecting the stored settings and stored settings can be read back without disturbing the DAC's output. FUNCTIONAL DIAGRAM
VPP 3 VDD 1 VREF H 14
Control of the CAT504 is accomplished with a simple 3 wire serial interface. A Chip Select pin allows several CAT504s to share a common serial interface and communication back to the host controller is via a single serial data line thanks to the CAT504's Tri-Stated Data Output pin. The CAT504 operates from a single 3-5 volt power supply drawing just a few milliwatts of power. When storing data in EEPROM memory an additional 20 volt low current supply is required. The CAT504 is available in the 0 to 70 C Commercial and -40 C to + 85 C Industrial operating temperature ranges and offered in 14-pin plastic DIP and Surface mount packages.
PIN CONFIGURATION
DIP Package (P)
VDD CLK VPP CS DI DO PROG
V OUT 3
SOIC Package (J)
VDD CLK VPP CS DI DO PROG 1 2 3 14 13 VREFH VOUT1 VOUT2 VOUT3 VOUT4 VREFL GND
1 2 3
14 13
PROG
7
PROGRAM CONTROL DAC 1
13
V 1 OUT
VREFH VOUT1 VOUT2 VOUT3 VOUT4 VREFL GND
DI
5 DAC 2 2 DATA REGISTER & EEPROM DAC 3
12
V OUT 2
CLK
SERIAL CONTROL
12 CAT 4 11 504 5 10 6 9 7 8
12 4 CAT 11 504 5 10 6 9 7 8
11
CS
4
DAC 4
10
V 4 OUT
SERIAL DATA OUTPUT REGISTER
6
DO
CAT504
8 GND 9 VREF L
(c) 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
1
Doc. No. 25048-0A 2/98 M-1
CAT504
ABSOLUTE MAXIMUM RATINGS* Supply Voltage VDD to GND ...................................... -0.5V to +7V VPP to GND ..................................... -0.5V to +22V Inputs CLK to GND ............................ -0.5V to VDD +0.5V CS to GND .............................. -0.5V to VDD +0.5V DI to GND ............................... -0.5V to VDD +0.5V PROG to GND ........................ -0.5V to VDD +0.5V VREFH to GND ........................ -0.5V to VDD +0.5V VREFL to GND ......................... -0.5V to VDD +0.5V Outputs D0 to GND ............................... -0.5V to VDD +0.5V VOUT 1- 4 to GND ................... -0.5V to VDD +0.5V RELIABILITY CHARACTERISTICS Symbol
VZAP(1) ILTH(1)(2)
Operating Ambient Temperature Commercial (`C' suffix) .................... 0C to +70C Industrial (`I' suffix) ...................... - 40C to +85C Junction Temperature ..................................... +150C Storage Temperature ....................... -65C to +150C Lead Soldering (10 sec max) .......................... +300C
* Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Absolute Maximum Ratings are limited values applied individually while other parameters are within specified operating conditions, and functional operation at any of these conditions is NOT implied. Device performance and reliability may be impaired by exposure to absolute rating conditions for extended periods of time.
Parameter
ESD Susceptibility Latch-Up
Min
2000 100
Max
Units
Volts mA
Test Method
MIL-STD-883, Test Method 3015 JEDEC Standard 17
NOTES: 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Latch-up protection is provided for stresses up to 100mA on address and data pins from -1V to VCC + 1V.
DC ELECTRICAL CHARACTERISTICS: VDD = 2.7V to 5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified Symbol Accuracy
INL Integral Linearity Error ILOAD = 250 nA, TR = C TR = I ILOAD = 1 A, TR = C TR = I ILOAD = 250 nA, TR = C TR = I ILOAD = 1 A, TR = C TR = I -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 2 2 0.5 0.5 1.5 1.5 LSB LSB LSB LSB LSB LSB LSB LSB
Parameter
Resolution
Conditions
Min
8
Typ
--
Max
--
Units
Bits
DNL
Differential Linearity Error
Logic Inputs
IIH IIL VIH VIL Input Leakage Current Input Leakage Current High Level Input Voltage Low Level Input Voltage VREFH Input Voltage Range VREFL Input Voltage Range VREFH-VREFL Resistance High Level Output Voltage Low Level Output Voltage IOH = - 40 A IOL = 1 mA, VDD = +5V IOL = 0.4 mA, VDD = +3V VIN = VDD VIN = 0V -- -- 2 0 2.7 GND -- VDD -0.3 -- -- -- -- -- -- -- -- 7k -- -- -- 10 -10 VDD 0.8 VDD VDD -2.7 -- -- 0.4 0.4 A A V V V V V V V
References
VRH VRL ZIN VOH VOL
Logic Outputs
Doc. No. 25048-0A 2/98 M-1
2
CAT504
DC ELECTRICAL CHARACTERISTICS (Cont.): VDD = 2.7V to 5.5V, VREFH = +VDD, VREFL = 0V, unless otherwise specified Symbol
FSO ZSO IL ROUT PSSR TCO TCREF
Parameter
Full-Scale Output Voltage Zero-Scale Output Voltage DAC Output Load Current DAC Output Impedance Power Supply Rejection VOUT Temperature Coefficient Temperature Coefficient of VREF Resistance Supply Current Programming Current Operating Voltage Range Programing Voltage Range
Conditions
VR = VREFH-VREFL VR = VREFH-VREFL VDD = +5V VDD = +3V ILOAD = 250 nA VREFH = +5V, VREFL = 0V VDD = +5V, ILOAD = 250nA VREFH to VREFL
Min
0.99 VR -- -- -- -- -- -- --
Typ
0.995 VR 0.005 VR -- -- -- -- -- 700
Max
-- 0.10 VR 1 20k 40k 1 200 --
Units
V V A LSB / V V/ C ppm / C
Analog Output
Temperature
Power Supply
IDD IPP VDD VPP Excludes VREF VPP = +19V -- -- 2.7 18 -- 200 -- 19 50 500 5.5 20 A A V V
AC ELECTRICAL CHARACTERISTICS: VDD = 2.7V to 5.5V, VREFH = +VDD, VREFL = 0V, unless otherwise specified Symbol Digital
tCSMIN tCSS tCSH tDIS tDIH tDO1 tDO0 tHZ tLZ tPROG tPS tCLKH tCLKL fC Minimum CS Low Time CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Output Delay to Low-Z Erase/Write Pulse Width PROG Setup Time Minimum CLK High Time Minimum CLK Low Time Clock Frequency DAC Settling Time to 1/2 LSB 150 100 0 50 50 -- -- -- -- 3 150 500 300 DC -- -- -- -- -- -- -- -- -- -- -- 400 400 5 -- -- -- -- 3 6 8 6 -- -- -- -- -- 150 150 -- -- -- -- -- -- 1 10 10 -- -- ns ns ns ns ns ns ns ns ns ms ns ns ns MHz s s pF pF
Parameter
Conditions
Min
Typ
Max
Units
CL = 100 pF see note 1
Analog
tDS CLOAD = 10 pF, VDD = +5V CLOAD = 10 pF, VDD = +3V VIN = 0V, f = 1 MHz(2) VOUT = 0V, f = 1 MHz(2)
Pin Capacitance
CIN COUT Input Capacitance Output Capacitance
NOTES: 1. All timing measurements are defined at the point of signal crossing VDD / 2. 2. These parameters are periodically sampled and are not 100% tested.
3
Doc. No. 25048-0A 2/98 M-1
TIMING MIN/MAX FROM TO
CAT504
to 2 3 4 5
1
PARAM NAME
t CLK H t CLK H Rising CLK edge to falling CLK edge Min
Doc. No. 25048-0A 2/98 M-1
CLK t CLK L Falling CLK edge to CLK rising edge t CSH t CLK L t CSS t CSH Falling CLK edge for last data bit (DI) to falling CS edge Rising CS edge to next rising CLK edge Min Min
A. C. TIMING DIAGRAM
t CSS
Min
CS t CSMIN t CSMIN Falling CS edge to rising CS edge t DIS Data valid to first rising CLK edge after CS = high Min
Min
t DIS
DI t DIH t DO0 t LZ t DO0 Rising CLK edge to end of data valid Min
4
t HZ t DO1 t PS t PROG 2 3 4 5
t DIH
Rising CLK edge to D0 = low Rising CS edge to D0 becoming high low impedance (active output)
Max (Max)
t LZ
DO t DO1 t HZ t PS Rising CLK edge to D0 = high Falling CS edge to D0 becoming high impedance (Tri-State) Rising PROG edge to next rising CLK edge Max (Max) Min
PROG t PROG Rising PROG edge to falling PROG edge Min
to
1
CAT504
PIN DESCRIPTION Pin
1 2 3 4 5 6 7 8 9 10 11 12 13 14
DAC addressing is as follows: Function
Power supply positive. Clock input pin EEPROM Programming Voltage Chip Select Serial data input pin. Serial data output pin. EEPROM Programming Enable Input Power supply ground. Minimum DAC output voltage. DAC output channel 4. DAC output channel 3. DAC output channel 2. DAC output channel 1. Maximum DAC output voltage.
Name
VDD CLK VPP CS DI DO PROG GND VREFL VOUT4 VOUT3 VOUT2 VOUT1 VREFH
DAC OUTPUT VOUT1 VOUT2 VOUT3 VOUT4
A0 0 1 0 1
A1 0 0 1 1
DEVICE OPERATION The CAT504 is a quad 8-bit Digital to Analog Converter (DAC) whose outputs can be programmed to any one of 256 individual voltage steps. Once programmed, these output settings are retained in non-volatile EEPROM memory and will not be lost when power is removed from the chip. Upon power up the DACs return to the settings stored in EEPROM memory. Each DAC can be written to and read from independently without effecting the output voltage during the read or write cycle. Each output can also be temporarily adjusted without changing the stored output setting, which is useful for testing new output settings before storing them in memory. DIGITAL INTERFACE The CAT504 employs a standard 3 wire serial control interface consisting of Clock (CLK), Chip Select (CS) and Data In (DI) inputs. For all operations, address and data are shifted in LSB first. In addition, all digital data must be preceded by a logic "1" as a start bit. The DAC address and data are clocked into the DI pin on the clock's rising edge. When sending multiple blocks of information a minimum of two clock cycles is required between the last block sent and the next start bit. Multiple devices may share a common input data line by selectively activating the CS control of the desired IC. Data Outputs (DO) can also share a common line because the DO pin is Tri-Stated and returns to a high impedance when not in use. CHIP SELECT Chip Select (CS) enables and disables the CAT504's read and write operations. When CS is high data may be
read to or from the chip, and the Data Output (DO) pin is active. Data loaded into the DAC control registers will remain in effect until CS goes low. Bringing CS to a logic low returns all DAC outputs to the settings stored in EEPROM memory and switches DO to its high impedance Tri-State mode. Because CS functions like a reset the CS pin has been equipped with a 30 ns to 90 ns filter circuit to prevent noise spikes from causing unwanted resets and the loss of volatile data. CLOCK The CAT504's clock controls both data flow in and out of the IC and EEPROM memory cell programming. Serial data is shifted into the DI pin and out of the DO pin on the clock's rising edge. While it is not necessary for the clock to be running between data transfers, the clock must be operating in order to write to EEPROM memory, even though the data being saved may already be resident in the DAC control register. No clock is necessary upon system power-up. The CAT504's internal power-on reset circuitry loads data from EEPROM to the DACs without using the external clock. As data transfers are edge triggered clean clock transitions are necessary to avoid falsely clocking data into the control registers. Standard CMOS and TTL logic families work well in this regard and it is recommended that any mechanical switches used for breadboarding or device evaluation purposes be debounced by a flip-flop or other suitable debouncing circuit.
5
Doc. No. 25048-0A 2/98 M-1
CAT504
VREF VREF, the voltage applied between pins VREFH andVREFL, sets the DAC's Zero to Full Scale output range where VREFL = Zero and VREFH = Full Scale. VREF can span the full power supply range or just a fraction of it. In typical applications VREFH andVREFL are connected across the power supply rails. When using less than the full supply voltage VREFH is restricted to voltages between VDD and VDD/2 and VREFL to voltages between GND and VDD/2. VPP When saving data to non-volatile EEPROM memory an external voltage of 18-20 volts must be applied to the VPP pin. This voltage need only be present during the programming cycle and may be removed or turned off the remainder of the time. While it is not necessary to remove or power down VPP between programming cycles, some power sensitive applications may choose to do so. In such cases, the VPP supply must be given sufficient time to come up and stabilize before issuing the PROG command. DATA OUTPUT Data is output serially by the CAT504, LSB first, via the Data Out (DO) pin following the reception of a start bit and two address bits by the Data Input (DI). DO becomes active whenever CS goes high and resumes its high impedance Tri-State mode when CS returns low. Tri-Stating the DO pin allows several 504s to share a single serial data line and simplifies interfacing multiple 504s to a microprocessor. WRITING TO MEMORY Programming the CAT504's EEPROM memory is accomplished through the application of an externally generated programming voltage, VPP, and the control signals: Chip Select (CS) and Program (PROG). With CS high, a start bit followed by a two bit DAC address and eight data bits are clocked into the DAC control register via the DI pin. Data enters on the clock's rising edge. The DAC output changes to its new setting on the clock cycle following D7, the last data bit. Programming is achieved by bringing PROG high for a minimum of 3 ms while supplying 18 to 20 volts to the VPP pin. PROG must be brought high sometime after the start bit and at least 150 ns prior to the rising edge of the clock cycle immediately following the D7 bit. Two clock cycles after the D7 bit the DAC control register will be ready to receive the next set of address and data bits. The clock must be kept running throughout the programming cycle. Internal control circuitry takes care of ramping the programming voltage for data transfer to the EEPROM cells. The CAT504's EEPROM memory cells will endure over 100,000 write cycles and will retain data for a minimum of 20 years without being refreshed. READING DATA Each time data is transferred into a DAC control register currently held data is shifted out via the DI pin, thus in every data transaction a read cycle occurs. Note, however, that the reading process is destructive. Data must be removed from the register in order to be read. Figure 2 depicts a Read Only cycle in which no change occurs in the DAC's output. This feature allows Ps to poll DACs for their current setting without disturbing the output voltage but it assumes that the setting being read is also stored in EEPROM so that it can be restored at the end of the read cycle. In Figure 2 CS returns low before the 13th clock cycle completes. In doing so the EEPROM's setting is reloaded into the DAC control register. Since this value is the same as that which had been there previously no change in the DAC's output is noticed. Had the value held in the control register been different from that stored in EEPROM then a change would occur at the read cycle's conclusion.
Figure 1. Writing to Memory
to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
Figure 2. Reading from Memory
to 1 2 3 4 5 6 7 8 9 10 11 12
CS NEW DAC DATA DI 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
CS
DI
1
A0
A1 CURRENT DAC DATA
CURRENT DAC DATA DO D0 D1 D2 D3 D4 D5 D6 D7
DO
D0
D1
D2
D3
D4
D5
D6
D7
PROG
PROG
Vpp
DON'T CARE
Vpp
DON'T CARE
DAC OUTPUT
CURRENT DAC VALUE NON-VOLATILE
NEW DAC VALUE VOLATILE
NEW DAC VALUE NON-VOLATILE
DAC OUTPUT
CURRENT DAC VALUE
NON-VOLATILE
Doc. No. 25048-0A 2/98 M-1
6
CAT504
TEMPORARILY CHANGE OUTPUT The CAT504 allows temporary changes in DAC's output to be made without disturbing the settings retained in EEPROM memory. This feature is particularly useful when testing for a new output setting and allows for user adjustment of preset or default values without losing the original factory settings. Figure 3 shows the control and data signals needed to effect a temporary output change. DAC settings may be changed as many times as required and can be made to any of the four DACs in any order or sequence. The temporary setting(s) remain in effect long as CS remains high. When CS returns low all four DACs will return to the output values stored in EEPROM memory. When it is desired to save a new setting acquired using this feature, the new value must be reloaded into the DAC control register prior to programming. This is because the CAT504's internal control circuitry discards the new data from the programming register two clock cycles after receiving it (after reception is complete) if no PROG signal is received. APPLICATION CIRCUITS
+5V
Figure 3. Temporary Change in Output
to 1 2 3 4 5 6 7 8 9 10 11 12 N N+1 N+2
CS
NEW DAC DATA 1 A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
DI
CURRENT DAC DATA DO D0 D1 D2 D3 D4 D5 D6 D7
PROG
Vpp
DON'T CARE
DAC OUTPUT
CURRENT DAC VALUE NON-VOLATILE
NEW DAC VALUE VOLATILE
CURRENT DAC VALUE NON-VOLATILE
+5V Ri
+15V
RF +15V
VDD CONTROL & DATA
VREF H
- +
-15V
VOUT
VDD CONTROL & DATA
VREF H
- +
-15V
VOUT
CAT504 OPT 504
GND VREF L
OP 07
CAT504 OPT 504
GND VREF L
OP 07
VOUT = VDAC
RF VOUT = (1 + ---) V DAC RI
Buffered DAC Output
Amplified DAC Output
DAC INPUT
+5V Vi Ri +15V VDD CONTROL & DATA VREF H RF
DAC OUTPUT CODE VDAC = ------ (VFS - VZERO ) + VZERO 255 VFS = 0.99 VREF VZERO = 0.01 VREF 255 ---- (.98 VREF ) + .01 VREF = .990 V REF 255 128 ---- (.98 V ) + .01 V = .502 V REF REF REF 255 127 ---- (.98 V ) + .01 V = .498 V 255 REF REF REF 1 (.98 V ---- ) + .01 V = .014 V 255 REF REF REF 0 ---- (.98 V ) + .01 V = .010 V REF REF REF 255
ANALOG OUTPUT
- +
-15V
VOUT OP 07
MSB 1111
LSB 1111
VREF = 5V R I = RF V OUT = +4.90V V = +0.02V OUT V = -0.02V OUT V = -4.86V OUT V = -4.90V OUT
CAT504 OPT 504
GND VREF L
1000 0111 0000
0000 1111 0001
VOUT = VDAC ( R i+ RF) -Vi R F Ri For R i = RF VOUT = 2VDAC -Vi
0000
0000
Bipolar DAC Output 7
Doc. No. 25048-0A 2/98 M-1
CAT504
APPLICATION CIRCUITS (Cont.)
VREF RC = ---------- 256 * 1 A +5V VREF VREFH Fine adjust gives 1 LSB change in V OFFSET VREF when VOFFSET = ------ 2
+5V +VREF VREFH
VDD
VDD
FINE ADJUST DAC
127RC + (+VREF ) - (VOFFSET ) RC = ---------------------- 1 A (-VREF ) + (VOFFSET+ ) Ro = ---------------------- 1 A
FINE ADJUST DAC
127RC
+V COARSE ADJUST DAC RC V OFFSET
COARSE ADJUST DAC
RC
+ -
GND
VREF L Ro -VREF VOFFSET
+V
+ -
-V
GND
VREF L
Coarse-Fine Offset Control by Averaging DAC Outputs for Single Power Supply Systems
Coarse-Fine Offset Control by Averaging DAC Outputs for Dual Power Supply Systems
28 - 32V
V+
I > 2 mA
15K 10 F
VDD CONTROL & DATA
VREF H
VREF = 5.000V
VDD
1N5231B
VREF H 5.1V 10K
CAT504 OPT 504
GND VREF L
LT 1029
CONTROL & DATA
CAT504 OPT 504
GND VREF L
+ - LM 324
MPT3055EL
OUTPUT 4.02 K 1.00K 10 F 35V 0 - 25V @ 1A
Digitally Trimmed Voltage Reference
Digitally Controlled Voltage Reference
Doc. No. 25048-0A 2/98 M-1
8
CAT504
APPLICATION CIRCUITS (Cont.)
+5V VREF VIN
1.0 F + - VDD VREF H
LM 339
10K +5V WINDOW 1 V REF WINDOW 1
OPT 504 CAT504
VPP
+ - + - +5V + 10K WINDOW 2
DAC 1
VOUT 1 WINDOW 2 VOUT 2
CS
-
DI
DAC 2
+ - +5V + 10K WINDOW 3 WINDOW 3
DO
-
PROG
DAC 3
+ - +5V + 10K WINDOW 4
VOUT 3 WINDOW 4 VOUT 4 WINDOW 5 GND WINDOW 5
CLK
-
DAC 4
+ - +5V + 10K
GND
VREF L
WINDOW STRUCTURE
-
Staircase Window Comparator
+5V VREF VIN
1.0 F
VDD
VREF H
+ - +5V + -
LM 339
10K WINDOW 1
OPT 504 CAT504
VPP
DAC 1
VREF H CS WINDOW 1
DI
DAC 2
+ - +5V + 10K WINDOW 2 VOUT 1
VOUT 2
WINDOW 2 VOUT 4
DO
-
PROG
DAC 3
VOUT 3 WINDOW 3
CLK
GND
DAC 4
+ - +5V + 10K WINDOW 3
WINDOW STRUCTURE
GND
VREF L
-
Overlapping Window Comparator
9
Doc. No. 25048-0A 2/98 M-1
CAT504
APPLICATION CIRCUITS (Cont.)
+5V 2.2K VDD VREF 4.7 A
LM385-2.5
+15V
ISINK = 2 - 255 mA
DAC
+5V 10K
+ -
10K
2N7000
391W 39 1W
1 mA steps
CONTROL & DATA
OPT 504 CAT504
DAC
+ 2N7000 -
5 A steps
GND
VREF L
5 meg
5 meg
3.9K
10K
10K
- + TIP 30
-15V
Current Sink with 4 Decades of Resolution
+15V
51K
+ TIP 29 -
10K +5V 10K
VDD
VREF H
5 meg
5 meg
39 1W 39 1W
DAC
CONTROL & DATA
-
OPT 504 CAT504
5 meg
+
5 meg
BS170P
1 mA steps
DAC
3.9K
GND
VREF L
- BS170P + LM385-2.5
5 A steps
-15V
ISOURCE = 2 - 255 mA
Current Source with 4 Decades of Resolution
Doc. No. 25048-0A 2/98 M-1
10
CAT504
APPLICATION CIRCUITS (Cont.)
+12V
1N914 1.0 F
10K +12V
74C14
1N914
.005 F VCC 13
0.1 F 2.5 F 0.47 F INPUT 1 20V IN5250B 2 IN 1 TREB CAP BASS CAP 4 8 0.39 F 3 1 19 10 0.01 F
Vpp
VDD
VZ
OUTPUT 1
OUT 1
CAT504 OPT 504
CHIP SELECT. PROGRAM DATA IN DATA OUT CLOCK 4 7 5 6 2 VREFH CS PROG DI DO CLK VOUT 1 VOUT 2 VOUT 3 VOUT 4 13 12 11 10 14
1.0 F 9 47K 47K 47K 47K 0.22 F 0.22 F 0.22 F 0.22 F 14 11 5 16 LOUDNESS VOLUME BALANCE TREBLE BASS
LM1040
1 BYPASS 7 18
47 F 10 F 10 F
VREFL GND
9 8 OUTPUT 2 15 OUT 2
0.47 F INPUT 2
23 3
IN 2 STEREO
BASS CAP TREB CAP GND GND
17 21 24
0.39 F
0.1 F 4.7K
0.01 F
22 ENHANCE
12
Digital Stereo Control
11
Doc. No. 25048-0A 2/98 M-1
CAT504
ORDERING INFORMATION
Prefix CAT
Device # 504
Suffix J I -TE13
Optional Company ID
Product Number
Package P: PDIP J: SOIC Temperature Range Blank = Commercial (0C to +70C) I = Industrial (-40C to +85C)
Tape & Reel TE13: 2000/Reel
Notes: (1) The device used in the above example is a CAT504JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
Doc. No. 25048-0A 2/98 M-1
12

▲Up To Search▲

Price & Availability of CAT504

	To Download CAT504 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .